Throughput enhancement for a universal host controller interface in a universal serial bus
US6684272B1 · kind B1 · utility
10Cited by
7References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1999 |
| Grant date | Jan 27, 2004 |
| Priority date | — |
| Expiry date | Dec 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A timing enhancement for a USB controller determines if a short data packet is present. If so, data is placed in a buffer. If the buffer is full, data is sent. If the buffer is not full, the system looks to see if more data is available, if so takes it, if not it sends whatever is available.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.