Method and apparatus for predictive flash memory erase and write times
US6684288B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 6, 2000 |
| Grant date | Jan 27, 2004 |
| Priority date | — |
| Expiry date | Aug 8, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/102
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NOR-gate architecture memory with an erase and write time table. The memory processor creates an erase and write time table in a table block. The table contains the most recent times for erase and write operations for each data block in the memory. When a storage operation is initiated, the processor accesses the table and estimates the amount of time it will take to perform the data storage operation and then communicates that back to a host computer. Each data storage operation results in a new table being created that is written into the data block. To save erase and write operations for the table block, the new table is written directly after the most recent table unless there is not enough space. An erase and write operation is only performed on the table block if there is not enough space for the new table.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.