Memory managing method used in adding memory and information processing apparatus
US6684312B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 1999 |
| Grant date | Jan 27, 2004 |
| Priority date | — |
| Expiry date | Feb 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information processing apparatus for allowing a memory to be added thereto while being powered. The apparatus comprises a processor, a first main memory initially connected, and a connecting switch. The switch connects the processor, the first main memory, and a second main memory to be added. Main memory management information in the first main memory includes the size of memory resources connected to the processor. A storage region in the connecting switch retains information about whether or not the processor is connected to each of the memories. The setup allows the apparatus to use the added memory without having to be restarted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.