Memory controller with programmable address configuration
US6684314B1 · kind B1 · utility
24Cited by
9References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 14, 2000 |
| Grant date | Jan 27, 2004 |
| Priority date | — |
| Expiry date | Oct 23, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1694
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller comprises a programmable interface coupled to address circuitry. The programmable interface receives a configuration signal into the memory controller indicating a selected address configuration. The address circuitry processes system addresses based on the selected address configuration to generate memory addresses. The configuration signal may also indicate a selected memory configuration, and the address circuitry processes the system addresses based on the selected memory configuration to generate memory device selections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.