Method of addressing sequential data packets from a plurality of input data line cards for shared memory storage and the like, and novel address generator therefor
US6684317B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2001 |
| Grant date | Jan 27, 2004 |
| Priority date | — |
| Expiry date | Jul 30, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3027
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A sequential data packet addressing technique and system, particularly adapted for shared memory output-buffered switch fabrics and related memories, using a ring of successive subaddress generators each assigning addresses for predetermined size data byte packets received in successive time slots, and creating therefrom super packets ordered based on arrival time; and sequentially allocating memory therefor in the shared memory without overlap among the packets and with no holes between adjacent packets, and assigning addresses for the individual packets in the super packets upon the assigning of an address in the memory for each super packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.