Method for detecting errors on parallel links
US6684363B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2000 |
| Grant date | Jan 27, 2004 |
| Priority date | — |
| Expiry date | Feb 11, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0045
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
System and method for rapidly calculating CRC values for messages including encoded bits is described. Tabularized CRC values are used in combination with a logical grid to quickly determine an appropriate CRC value of a message. This determination can take into account encoded inversion bits in the message. A collection of pre-calculated CRC values are arranged in a single-column table and then implemented with selected bits of a message by superimposing the bits in each CRC value onto a logical grid. Vertical lines of the grid are associated with 30 exclusive OR (XOR) gates and horizontal lines are associated with bits in an 88-bit message (or the 30 bits of a CRC value or with 8 bits of a sequence number). Through this grid, the inputs to the XOR gates are determined, thereby facilitating rapid calculations of CRC values due to the high processing speeds possible in XOR gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.