Timing budget designing method
US6684374B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2001 |
| Grant date | Jan 27, 2004 |
| Priority date | — |
| Expiry date | Nov 7, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When a logical block is built in an LSI logic design stage, a maximum delay value between pins of a block is set based on a designer's estimation, or information of a netlist after the netlist is generated. Pins can be grouped. A delay value in a connection between pins is represented by the largest value. Additionally, a plurality of internal memory elements within a logical block are represented by one or a plurality of internal latches. Also as a delay value between a pin and an internal latch, or between an internal latch and a pin, the largest value is selected from among a plurality of delay values, and set as a representative value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.