Multi-level integrated circuit for wide-gap substrate bonding
US6686642B2 · kind B2 · utility
10Cited by
12References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2001 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Jun 11, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An integrated circuit includes a substrate having an etched surface and a non-etched surface. The etched surface contains circuit elements and the non-etched surface contains a bonding surface. The non-etched surface is located at a predetermined height from the etched surface. Bonding this integrated circuit with another substrate creates a wide-gap between the substrates that is preferably evacuated and hermetically sealed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.