System and method for a high speed, bi-directional, zero turnaround time, pseudo differential bus capable of supporting arbitrary number of drivers and receivers
US6686774B1 · kind B1 · utility
2Cited by
7References
5Claims
0Family size
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Key dates
| Filing date | Jul 19, 2001 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Jul 19, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4077
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for high speed bussing in microprocessors and microelectronic devices is disclosed. The method and system implement a type of differential bus with distributed bus pre-charge units designed to decrease bus pre-charge time. The method and system utilize a universal self-tracking clock signal to determine the minimum required bus pre-charge time. The time saved by decreasing the bus pre-charge time can be directly applied to the bus evaluation period thereby increasing system performance and reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.