Image display apparatus and method
US6686894B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2002 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Jun 29, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/02
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An image display apparatus and method having a synchronizing signal decimation circuit for performing decimation of vertical synchronizing signals, an image decimation circuit for performing decimation of image data, an image scale-up circuit for scaling up the decimated image data, a display panel for displaying an image, a driving circuit for causing the display panel to sequentially display individual frames of image according to the scaled-up image data in synchronization with the decimated vertical synchronizing signals, and a controller having information of a scaling factor of the image scale-up circuit, vertical synchronizing signals to be discarded by the synchronizing signal decimation circuit, and image data to be discarded by the image decimation circuit. The controller controls operation of the synchronizing signal decimation circuit, the image decimation circuit, the image scale-up circuit, and the driving circuit according to the information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.