Reference cells with integration capacitor
US6687177B2 · kind B2 · utility
4Cited by
7References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 1, 2002 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Apr 1, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM having integration capacitors coupled to dummy memory cells of a folded bitline arrangement is disclosed. The dummy memory cells are identical to normal memory cells, and store a midpoint voltage via equalisation between the dummy memory cell having a logic “1” voltage potential and the dummy memory cell having a logic “0” voltage potential. The integration capacitor shares charge with both dummy cell storage capacitors during an equalisation operation to compensate for bitline voltage differences during various access cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.