Delay-locked admission control scheme in communications networks
US6687223B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2000 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Jan 11, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L47/826
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A connection admission control mechanism for packet, circuit, or hybrid packet and circuit networks whereby the signaling message (i.e., “query”) delay in a control channel of a network switch is maintained (i.e., “locked”) in a timed control interval at a desired level using feedback parameters relating to an estimated current amount of delay in the packet network switch during one or more previous timed control intervals, to guarantee or closely achieve a desired signaling message or query delay performance. The processing delay of the network is bound or “locked” at a desired delay performance level based on substantially real-time estimation or measurement of the current signaling message delays of queries or call control packet streams during one or more previous control intervals. Thus, connection processing is robust against variations in traffic intensity and/or processing capabilities of the switch, and a single QoS measure or specification can be applied to the network switch. Because of the resemblance to a phase locked loop (PLL) in hardware timing acquisition techniques, the technique is referred to herein as Delay-Locked Admission C…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.