Single chip VLSI implementation of a digital receiver employing orthogonal frequency division multiplexing
US6687315B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2001 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Jan 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2662
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The invention provides a single chip implementation of a digital receiver for multicarrier signals that are transmitted by orthogonal frequency division multiplexing. Improved channel estimation and correction circuitry are provided. The receiver has highly accurate sampling rate control and frequency control circuitry. BCH decoding of tps data carriers is achieved with minimal resources with an arrangement that includes a small Galois field multiplier. An improved FFT window synchronization circuit is coupled to the resampling circuit for locating the boundary of the guard interval transmitted with the active frame of the signal. A real-time pipelined FFT processor is operationally associated with the FFT window synchronization circuit and operates with reduced memory requirements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.