Phase lock loop (PLL) clock generator with programmable skew and frequency
US6687320B1 · kind B1 · utility
38Cited by
5References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 27, 1999 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | May 27, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase lock loop (PLL) clock generator with programmable frequency and skew is provided in the present invention, in which frequency of clock signals generated can be dynamically changed and skew of the clock signals generated can be dynamically adjusted by a computer program. Also, the signal skew due to the change of loading can be compensated. Therefore, the PLL clock generator based on a closed-loop configuration can better control the skew of clock signals to provide higher stability and durability to the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.