Dual mode clock alignment and distribution device
US6687322B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2000 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Jun 3, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides a dual mode clock alignment device including a clock buffer cell, a PLL, and a first set and second set of buffers. The clock buffer cell is arranged to receive a first clock and delays the first clock. The PLL is arranged to receive the delayed first clock from the clock buffer and outputs a second clock. The first and second sets of buffers are arranged to receive the delayed first clock from the clock buffer cell for operating in a first clock mode. The first and second sets of buffers are further arranged to receive the second clock from the PLL for operating in a second clock mode. In this arrangement, the first set of buffers delays the received clock by a first delay to output a third clock and the second set of buffers delays the delayed clock by a second delay to output a fourth clock. When operating in the second clock mode, the first, third, and fourth clocks are all aligned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.