ATAPI command receiving method
US6687763B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2001 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Apr 4, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3879
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides an ATAPI command receiving method in which the CPU 72 can quickly correspond to other processings without expending much time for capturing data, as well as it can be prevented that data which are being captured by the CPU should be destroyed. In this ATAPI command receiving method, when an ATAPI protocol control LSI 71 comprising a shared register storage area 711 (including a data FIFO 7112 for containing command packets) for receiving a command from the host computer via an ATA bus 2, and a buffer memory 712 which can be used as a RAM of a CPU 72 receives a command, shared register values (including a command packet value) are stored at a storage destination address in the buffer memory 712 which is designated by the CPU 72, when the data storage permission is given by the CPU 72.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.