Methods and apparatuses for non-equivalence checking of circuits with subspace
US6687882B1 · kind B1 · utility
24Cited by
26References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2002 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Mar 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for designing integrated circuits. In one exemplary method, matched registers between the two netlists are determined. The matched registers become cut off points to generate primary inputs and outputs. When there are one or more unmatched registers between the first netlist and the second netlist, the unmatched registers are pushed to the primary inputs or outputs using retiming. At the primary inputs, a subspace generator is used to generate subspaces. The subspaces are used to identify non-equivalences between the first and second netlists. Other features and embodiments are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.