Method of optimizing high performance CMOS integrated circuit designs for power consumption and speed
US6687888B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 14, 2002 |
| Grant date | Feb 3, 2004 |
| Priority date | — |
| Expiry date | Mar 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of optimizing speed and predicted power of integrated circuit designs includes creating a machine representation representing devices of the integrated circuit design, where for each device in a path of the integrated circuit, the representation includes device size information and device type information. The device type information includes selection between at least one fast-but-leaky type and at least one slow-but-not-leaky type. A global optimization is then performed, wherein substitutions of both device type and device size are performed on the machine representation in each iteration. Substituted representations are evaluated for speed and power consumption.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.