System and method for shifting the phase of a clock signal
US6690223B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 27, 2001 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | Dec 27, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00286
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An embodiment of this invention pertains to a digital circuit that shifts the phase of a clock signal. In this embodiment, multiple delay units, e.g., buffers, shift the clock signal multiple times and store a level of the clock signal within corresponding memory devices, e.g., flip-flops when triggered by the phase shifted clock signals. These levels may be at a high level (e.g., the clock signal has the value “1”) or a low level (e.g., the clock signal has the value “0”). A “phase selection table” stores multiple entries, each of the entries includes multiple clock level values. Each of the entries specifies values used to determine when the phase shifted clock signals transition from the high level to the low level. This transition point signifies a 180 degree phase shift. Using this transition point, other phase shifts can be determined. Each of the entries specifies a particular one of the multiple delay units that provides the desired clock phase shift amount given different transition points occurring due to different operating conditions. The output from the specified delay unit is transmitted to an external device that uses the clock sig…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.