Delay circuit with current steering output symmetry and supply voltage insensitivity
US6690242B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2002 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | Jan 29, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00208
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for providing a symmetrical output signal to a communication system. The circuit includes an input circuit (22 and 24) for receiving an input signal and a symmetry circuits (205 and 210) advantageously configured to provide an output signal exhibiting a symmetrical rising and falling edge waveform in response to the received input signal. An integrated power source (Is) provides current to a common node (N1) in which current is advantageously steered to each half circuit (22, 205 and 24, 210) to reduce voltage variation on the common node during voltage transition of the input signal, hence, reducing current fluctuation from the current source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.