CMOS whole chip low capacitance ESD protection circuit

US6690557B2 · kind B2 · utility

Assignee

• Faraday Technology Corp. · TW

Inventors

• Kei-Kang Hung · Changhua City, TW
• Chien-Hui Chuang · Taipei, TW

Key dates

• Filing date: Dec 4, 2001
• Grant date: Feb 10, 2004
• Expiry date: Jun 2, 2022

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/713

Abstract

A low capacitance electrostatic discharge circuit (ESD) for a built-in CMOS chip capable of protecting an internal circuit within the chip. A first voltage source and a second voltage source are provided to the electrostatic protection circuit. The ESD circuit is coupled to a bonding pad and the internal circuit. The ESD protection circuit includes a first diode series, a second diode series, a first control circuit, a third diode series, a first silicon-controlled rectifier (SCR), a second control circuit, a fourth diode series and a second SCR. The ESD circuit utilizes the control circuits to initiate substrate triggering so that the triggered voltage of the SCR is lowered and holding voltage of the SCR during conduction in increased. Consequently, the entire chip is protected and input capacitance of the circuit is reduced.