Effective gate-driven or gate-coupled ESD protection circuit
US6690561B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2001 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | May 16, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H3/006
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An ESD protection circuit, arranged between a first and second potential terminals, has a RC branch, a voltage adjuster circuit, and an ESD discharge transistor. The RC branch includes a resistor and a capacitor series connected from the first to the second potential terminal. The voltage adjuster circuit has a plurality of inputs connected to the RC branch, and the first and second potential terminals, and an output connected to a gate of the ESD discharge transistor to adjust the gate voltage thereof for obtaining a uniform turn on and optimal ESD robustness. The voltage adjuster circuit mainly includes a plurality of transistors that enable to effectively adjust the gate voltage with respect to high level of ESD stress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.