Power inverter designed to minimize switching loss
US6690593B2 · kind B2 · utility
11Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2002 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | Sep 18, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02B70/10
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A power inverter for a polyphase load such as an AC motor is provided which is designed to minimize an on-off switching loss of transistors installed in the inverter. The inverter works to disenable switching operations of the transistors for each phase in a first cycle during which a corresponding output current is high in level and partially disenable the switching operations in a second cycle following the first cycle during which the corresponding output current is middle in level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.