Synchronizing clock enablement in an electronic device
US6691071B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 2002 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | May 13, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of synchronizing enablement of a common clock for a main and a second processor in an electronic device having a low-power mode includes a first step of completing a communication activity by the main processor. A next step includes monitoring a clock enable signal from the second processor. A next step includes comparing the timing of the second processor with the known timing of the main processor if the second processor does not have the clock enabled in the monitoring step. A next step includes calculating the the timing needed to synchronize the clock enablement by the second processor to that of the main processor. A next step includes powering up and powering down the second processor under control by the main processor to synchronize the periodic timing of the second processor to that of the main processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.