Accelerated montgomery multiplication using plural multipliers
US6691143B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 4, 2001 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | Jul 8, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Montgomery multipliers and methods modular multiply a residue multiplicand by a residue multiplier to obtain a residue product, using a scalar multiplier, a first vector multiplier and a second vector multiplier. A controller is configured to control the scalar multiplier, the first vector multiplier and the second vector multiplier, to overlap scalar multiplies using a selected digit of the multiplier and vector multiplies using a modulus and the multiplicand. The scalar multiplier is configured to multiply a least significant digit of the multiplicand by a first selected digit of the multiplier, to produce a scalar multiplier output. The first vector multiplier is configured to multiply the scalar multiplier output by a modulus, to produce a first vector multiplier output. The second vector multiplier is configured to multiply a second selected digit of the multiplier by the multiplicand, to produce a second vector multiplier output. An accumulator is configured to add the first vector multiplier output, and the second vector multiplier output, to produce a product output. The latency of Montgomery multiplication thereby can be reduced to nearly the latency of a single scalar mul…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.