Second transfer logic causing a first transfer logic to check a data ready bit prior to each of multibit transfer of a continous transfer operation
US6691183B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 18, 1999 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | May 18, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4291
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital device interface for transferring information between a processor and a control device includes a first serial peripheral interface (SPI), e.g., with “data in,” “data out” and “clock” ports, in serial communication with a second SPI. The first SPI can be coupled to, and associated with, the processor; the second SPI, with the control device. A first transfer logic section, e.g., a shift register engine, transfers bytes, word, longwords or other multi-bit datum between the processor and the control device. A second transfer logic section effects a transfer transaction between the processor and the control device—that is, the transfer of plural multi-bit datum relating to a common data access operation or a common data generation operation. For sensor-type control devices, such a transaction may include, for example, the “continuous” transfer of data sensed by the device. For a servo, actuator, or the like, the transaction may include, for example, a stream of set points or other control data generated by the processor (and/or its related data stores) for application to the control device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.