Transaction retry in multi-processor system
US6691191B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2000 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | Oct 21, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information-processing device includes a bus, a plurality of processors connected to the bus, and a bus-control unit which detects whether an excessively retried address transaction is present. Each of the processors includes an issuing unit which issues address transactions, a monitoring unit which communicate with the bus-control unit, and a retry-control unit which controls the issuing unit to suspend or restrain issuance of address transactions, other than the excessively retried address transaction, and to put an already issued address transaction in a status of compulsory retry if the monitoring unit is informed of a presence of the excessively retried address transaction by the bus-control unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.