Circuit and method for hardware-assisted software flushing of data and instruction caches
US6691210B2 · kind B2 · utility
2Cited by
3References
20Claims
0Family size
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Inventors
Key dates
| Filing date | Dec 29, 2000 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | Jun 12, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache flush controller, and an associated method, selectably flushes a memory cache of a data processor. The cache flush controller operates at a memory bus level of the data processor and operates to flush a selected line, or lines of the memory cache by writing arbitrary, selected values to the selected line or lines of the memory cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.