Method and apparatus for reducing power consumption
US6691215B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2000 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | Apr 3, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system is provided. The memory system is comprised of a memory, a clock signal generator, a phase locked loop circuit, and a bypass circuit. The clock signal generator produces a first clock signal. The clock signal generator has a first mode of operation in which the first clock signal has a first frequency and a second mode of operation in which the first clock signal has a second frequency. The phase locked loop circuit is associated with the memory and adapted for receiving the first clock signal and providing a synchronized second clock signal to the memory. The bypass circuit is adapted to deliver the first clock signal to the memory in the second mode of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.