Method and apparatus for 24-bit memory addressing in microcontrollers
US6691219B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2001 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | Feb 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7814
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides an 8-bit microcontroller capable of supporting expanded addressing capability in one of three address modes. The microcontroller operates in either the traditional 16-bit address mode, a 24-bit paged address mode or in a 24-bit contiguous address mode based on the setting of a new Address Control (ACON) Special Function Register (SFR). The 24-bit paged address mode is binary code compliant with traditional compilers for the standard 16-bit address range, but allows for up to 16M bytes of program memory and 16M bytes of data memory to be supported via a new Address Page (AP) SFR, a new first extended data pointer (DPX) SFR and a new second extended data pointer (DPX1) register. The 24-bit contiguous mode requires a 24-bit address compiler that supports contiguous program flow over the entire 24-bit address range via the addition of an operand and/or cycles to either basic instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.