Bus mastering debugging system for integrated circuits
US6691266B1 · kind B1 · utility
34Cited by
6References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 15, 1999 |
| Grant date | Feb 10, 2004 |
| Priority date | — |
| Expiry date | Oct 15, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/317
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit includes a debugging unit which uses a multi-master general purpose bus within the IC to perform debugging functions. The storage elements of the IC are mapped into the address space of the general purpose bus. The debugging unit can operate as a bus master and read from or write to the storage elements of the integrated circuit directly with the general purpose bus. Thus, the integrated circuit can be rapidly configured for testing and debugging. Furthermore, the debugging unit can work with a breakpoint unit on the IC to detect and analyze specific situations on the IC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.