Power sequencing and ramp rate control circuit
US6693410B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 16, 2002 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | Dec 16, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/575
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
Power control circuits that control the power sequencing and ramp rate of voltages applied to integrated circuits are disclosed. In one embodiment, a power control circuit comprises a delay resistor, a delay capacitor and an input transistor. The delay resistor is adapted to be coupled to an input power supply. The delay capacitor is coupled in series with the delay resistor. The input transistor has an emitter that is adapted to be coupled to the input power supply through the delay resister. The input transistor conducts current when a voltage across the delay capacitor rises above a selected voltage threshold of the input transistor. A power source is applied to a load in response to the conduction of the input transistor which is delayed by the time it takes to charge the delay capacitor to the selected voltage threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.