Patent · US Expired

Configuration for identifying contact faults during the testing of integrated circuits

US6693447B1 · kind B1 · utility

5Cited by

5References

8Claims

0Family size

Assignee

Siemens Aktiengesellschaft · DE

Inventors

Dominique Savignac · Ismaning, DE
Frank Weber · San Diego, US
Norbert Wirth · Unterschleißheim, DE

Key dates

Filing date	Mar 26, 1999
Grant date	Feb 17, 2004
Priority date	—
Expiry date	Aug 13, 2020

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/2884
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A configuration for identifying contact faults during the testing of integrated circuits with a multiplicity of pins which protrude from a housing and are connected to respective pads on a semiconductor body of the integrated circuit. Pull-up or pull-down devices are connected between respective pads and input buffers and in each case hold the pads at a high or low potential by impressing a holding current, if contact has not been made with a pin associated with the pad during testing, the result being that activation of the circuit section connected to the pin is avoided.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.