Distributed RAM in a logic array
US6693454B2 · kind B2 · utility
10Cited by
17References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 17, 2002 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | May 17, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Distributed RAM in a logic array. A single, customizable, logic array fabric provides both gate array logic and RAM functionality simultaneously while substantially maximizing the amount of configurable metal for routing. The extra semiconductor area in the cells of a metal limited device is used to implement general purpose RAM. Common select lines and read/write lines for the RAM are embedded in the base cells so that the configurable metal (whether via or actual metal layer) over the RAM can be used for routing logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.