Interconnection network for a field programmable gate array
US6693456B2 · kind B2 · utility
47Cited by
5References
29Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 3, 2001 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | Aug 3, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An interconnection network architecture which provides an interconnection network which is especially useful for FPGAs is described. Based upon Benes networks, the resulting network interconnect is rearrangeable so that routing between logic cell terminals is guaranteed. Upper limits on time delays for the network interconnect are defined and pipelining for high speed operation is easily implemented. The described network interconnect offers flexibility so that many design options are presented to best suit the desired application.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.