Method and system for improving speed in a flip-flop
US6693459B2 · kind B2 · utility
14Cited by
7References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2002 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | Jan 22, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356139
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides techniques, including a system and method, for improving speed in a flip-flop, having a pre-charged stage coupled to an evaluation stage. In one exemplary embodiment delay is reduced by using a conditional rather than an unconditional keeper, where the conditional keeper has the function of a keeper only under certain conditions. In some embodiments there is a conditional keeper in either the pre-charged stage or the evaluation stage or both stages. Another embodiment provides for the combining of the evaluation stage with one or more external logic functions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.