Method and system for low power, low jitter, wide range, self-adaptive multi-frequency phase locked loop
US6693496B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 13, 2002 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | Mar 13, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A self-adaptive method for controlling a self-biased PLL system is disclosed. The method comprises providing an application-dependent input frequency; and providing an application-dependent number N representing the ratio between the output frequency and the application-dependent input frequency to the PLL system. In a system and method in accordance with the present invention, the bandwidth and damping factor are tracked, not only with the input frequency but with the divider ratio as well. Therefore, jitter is minimized for any operating condition (i.e., input frequency variations [N]). The charge-pump current is made to be proportional to the VCO current ID and inversely proportional to the frequency range N; and the loop filter resistor is made to be inversely proportional to the square root of the VCO current ID and proportional to N. In so doing, the bandwidth and damping factors can be tracked more comprehensively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.