Multi-channel bit-serial analog-to-digital converter with reduced channel circuitry
US6693575B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2002 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | May 17, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/56
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A multi-channel bit-serial analog-to-digital converter with reduced channel circuitry is described herein in which a one-bit comparator circuit is split between a first part located within an input channel and a second part located outside the input channel. The external part of the comparator and the one-bit latch are shared by a plurality of input channels. In the preferred embodiment, a two-dimensional sensor array of pixel elements is fabricated in a single integrated circuit. Each of the pixel elements is an input channel which comprises a photodetector and the front-end part of the one-bit comparator. The external part of the comparator and the one-bit latch are formed in the periphery of the sensor array and are shared by a group of pixel elements, such as a column of pixel elements. In one embodiment, by connecting the output of an inverter to the control signal terminal of the comparator, the comparator can also be used as a buffer for analog readout. This creates an analog read port for minimum amount of circuitry increase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.