Digital-to-analog DAC-driven phase-locked loop PLL with slave PLL's driving DAC reference voltages
US6693987B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 5, 2000 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | Jul 6, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/23
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generator uses two PLL loops and a digital-to-analog converter (DAC) to generate a variable output frequency from a single fixed-frequency reference clock. Each PLL loop receives the reference clock and phase-compares it with a feedback clock. The feedback clock in one loop is slightly faster in frequency than the feedback clock in the second loop. The input voltages to voltage-controlled oscillators (VCOs) in the two loops thus vary slightly. A DAC is connected between the two VCO inputs. The DAC's two reference-voltage inputs are connected to these VCO inputs. The DAC's output voltage is selected from within the voltage range between the two VCO voltages by a digital code-word input to the DAC. The DAC's output voltage is input to a final VCO that generates the variable output frequency. The output frequency is varied by selecting the digital code-word input to the DAC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.