Configuration bus reconfigurable/reprogrammable interface for expanded direct memory access processor
US6694385B1 · kind B1 · utility
31Cited by
9References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2000 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | Apr 23, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The configuration bus interconnection protocol provides the configuration interfaces to the memory-mapped registers throughout the digital signal processor chip. The configuration bus is a parallel set of communications protocols, but for control of peripherals rather than for data transfer. While the expanded direct memory access processor is heavily optimized for maximizing data transfers, the configuration bus protocol is made to be as simple as possible for ease of implementation and portability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.