Cache memory with data transfer control and method of operating same
US6694407B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2001 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | Oct 24, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory (35) has a logical organisation in which its memory space is divided into sub-sections or partitions (P). This permits different data objects to be allocated to different partitions during the operation of the cache memory (35). Commands led used by the cache memory (10) may contain an extra parameter which is used to identify the appropriate partition within the cache memory (35). The parameter is extracted from the command by a decoder (37) and is passed to a specific line of an equator set (38) which contains identifiers which determine the partition to be used. To minimise data collisions for a given partition size, a stride may be defined which expresses the separation of addresses and from which a mapping function can be selected which covers all addresses in the cache memory (35) in an efficient way.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.