Scalable replacement method and system in a cache memory
US6694408B1 · kind B1 · utility
Inventors
Key dates
| Filing date | May 1, 2000 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | May 1, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/124
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a system and method for executing a replacement selection algorithm embedded in each associativity of a cache memory architecture. Each associativity in a cache has an internal control logic that governs the process for replacing a cache line when a certain condition occurs, such as a presence of a TagHit. A designated set of control signals is used in an associativity control logic for corresponding with an external control logic. An associativity control logic within an associativity provides an internal capability to determine whether a TagHit condition occurs as well as volunteering the associativity for replacement. The preferred replacement algorithm is implemented using an approximation to Not the Most Recently Used Associativity (NMRU).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.