Memory hole modification and mixed technique arrangements for maximizing cacheable memory space
US6694418B2 · kind B2 · utility
2Cited by
4References
45Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2001 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | Dec 20, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Cache defining arrangements for maximizing cacheable memory space, including a mixed technique scheme using a bottom-up scheme defining a first non-memory-hole portion using mainly substantially additive blocks of cacheable space, and a top-down scheme defining a second non-memory-hole portion by defining an oversized block of cacheable space and using mainly substantially subtractive blocks of cacheable space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.