Cache memory bank access prediction
US6694421B2 · kind B2 · utility
9Cited by
6References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 1999 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | Dec 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0846
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache bank prediction unit is provided for use in a processor having a plurality of cache memory banks. The cache bank prediction unit has an input port that receives an instruction. The cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of cache banks is associated with the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.