System for synchronizing a microprocessor with an asynchronous event by detecting an awaited event occurs and immediately applying load signal to a counter thereafter
US6694446B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 3, 2000 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | Feb 27, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4484
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a microprocessor (10) comprising a counter (TMR) to measure a time interval as a function of a counting instruction value (VAL) and a counting clock signal (H2). According to the invention, the microprocessor (10) comprises wired logic detection means (EVTDET) for the detection of at least one awaited event (E1, E2, E3), these means being arranged for the immediate application of a signal (LOAD) for the loading of a counting instructed value (VAL1, VAL2) to said counter when the awaited event takes place. Application especially to the management of a transmission of asynchronous data at a high bit rate in contactless chip cards.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.