Reed-solomon encoder and decoder
US6694476B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 2000 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | Feb 10, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1525
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semi-parallel forward error correction system. In one embodiment the forward error correction system includes a semi-parallel Reed-Solomon encoder and a semi-parallel Reed-Solomon decoder. Information symbols comprised of bytes are provided eight bytes in parallel to an encoder which in parallel forms eight bytes of a nonsystematic code word. On decoding, a code word is provided to a time multiplexed syndrome generator and key equation solver. An error locator polynomial from the key equation solver and the syndromes from the syndrome generator are provided to an error location and error magnitude unit, which includes a plurality of polynomial evaluator units which process an error locator polynomial in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.