Test interface for a configurable system on-chip
US6694489B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2000 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | Jan 30, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318342
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of communicating with a configurable system-on-chip via a test interface is described. First, an interface is coupled to a configurable system-on-chip and a first command is sent to the interface from a tester. The next command execution is then blocked. Next, the first command is executed in the configurable system-on-chip. Data is then output from the configurable system-on-chip and written to a register in the interface. The data output includes a ready bit. Next, the data from the register is read. The first bit read is an asserted ready bit. The next command execution is then enabled. When the asserted ready bit is received in the tester, the tester sends a second command to the interface. The second command is then executed in the configurable system-on-a-chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.