Flexible preamble processing for detecting a code sequence
US6694496B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2001 |
| Grant date | Feb 17, 2004 |
| Priority date | — |
| Expiry date | Sep 24, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0611
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An architecture and method for flexible preamble processing is disclosed herein. The preamble processing engine detects a code sequence in input, where the code sequence is a sum of a first code sequence and a second code sequence The preamble processing engine includes a data input line, a code input line, a despreader, and a plurality of memory registers. The code input selectively receives the first code sequence or the second code sequence, the first code sequence having a period longer than a period for the second code sequence. The despreader is coupled to the data input line and the code input line. The despreader producing a despread result between the first code sequence and the input data. Lastly, the plurality of memory registers, which are coupled to the despreader, each stores only a portion of the despread results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.