Semiconductor structure
US6696760B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 10, 2002 |
| Grant date | Feb 24, 2004 |
| Priority date | — |
| Expiry date | Dec 10, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a method of providing a substrate, the substrate having a first metal line and a second metal line isolated horizontally by a dielectric; forming an etch stop layer over the substrate; reducing thickness of the etch stop layer over the first metal line, leaving thickness unchanged over the second metal line; forming an interlayer dielectric (ILD) over the etch stop layer; and removing the ILD over the second metal line. The present invention further discloses a structure that includes a substrate; a first metal line and a second metal line located over the substrate; a dielectric located over the substrate adjacent to the first metal line and the second metal line; an etch stop layer located over the first metal line, the second metal line, and the dielectric, the etch stop layer being thicker over the second metal line; and a via located over the thicker etch stop layer over the second metal line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.