Semiconductor memory device input circuit
US6696862B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2002 |
| Grant date | Feb 24, 2004 |
| Priority date | — |
| Expiry date | May 19, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device input circuit including a clock selection portion. The clock selection portion receives an internal clock signal before a data strobe signal is enabled. The input circuit includes a plurality of input buffers, a clock selection circuit, a calibration circuit, and a plurality of data registers. The clock selection circuit receives a selection signal that is maintained at a first logic level for a predetermined time from the time when power is initially supplied and has a second logic level. The clock selection circuit selects a first clock signal and outputs the first clock signal as a second clock signal when the selection signal is maintained at the first logic level. The clock selection circuit selects the data strobe signal and outputs the data strobe signal as the second clock signal when the selection signal is maintained at the second logic level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.